Cohort 2 · Applications open
RRISC-V
Ifor Indian
SSemiconductor
EEducation

A 6-week live program that trains you to design, implement, and verify a RISC-V processor from the ground up — using only open-source tools.

Apply for RISE → View curriculum
6 weeks
Duration
Live
Online sessions
Fully
Funded seats available
100%
Open-source tools
Why RISE

India's chip ambitions
need RISC-V engineers.

RISC-V is the open ISA at the center of India's semiconductor push — from national initiatives to global chip startups. RISE closes the training gap.

ISA
Architecture-first, not tool-first
You learn why RISC-V works the way it does — instruction encoding, the extension model, privilege levels — before touching RTL.
RTL
Real designs, not toy examples
You write and simulate a pipelined processor. Every lab adds to a core that runs real software by week six.
SoC
System-level perspective
Buses, memory maps, interrupts — you see how a processor core lives inside a complete SoC, not just in isolation.
OSS
Entirely open-source toolchain
Verilator, Spike, QEMU, GTKWave — everything free. No licenses, no institutional access required.
6
Live training weeks
∞
No ISA royalties
6+
Hands-on lab modules
1
Capstone RISC-V core
Tools you'll use
VerilatorSpike ISSQEMUGTKWaveriscv-gccSystemVerilogriscv-testsOpenOCD
What you'll learn

Six weeks. Built to stack.

Each module builds directly on the last — from ISA fundamentals to a verified pipelined core running real software.

Week One
Logic Design & Verilog Foundations
  • Mux, demux, logic design
  • Adders, multipliers, flip-flops
  • Logic design modules, gates, mux, demux, FIFO
  • Verilog: registers, adder, multiplier, verification
Theory + Lab
Week Two
ISA & RV32I Processor Basics
  • ISA basics and simple RISC processor design
  • RISC-V instruction set and RV32I
  • Control logic and simple RISC processor design part 2
  • Instruction execution flow and datapath design
Hands-on RTL
Week Three
Pipelining & Hazards
  • Pipelining: interlock, bypass, structural, data, and control hazards
  • Execution and interrupts, branch delay slot
  • Complex in-order pipelines: CDC6600 and MIPS R4000
Core RTL
Week Four
Memory Hierarchy
  • Memories and caches: direct-mapped and set-associative
  • Replacement policy, write policy, cache performance, write buffer
  • Multi-level caches and address translation
  • Base-and-bound, paged memory, TLBs, page faults, virtual address caches
System Design
Week Five
Out-of-Order Execution
  • Scoreboarding and complex in-order pipeline concepts
  • Tomasulo's architecture, out-of-order issue, and register renaming
  • Unified physical register file and in-order commit
  • Branch prediction: BHT and Branch Target Buffer
Advanced Architecture
Week Six
Parallelism & Capstone
  • VLIW processors, loop unrolling, software pipelining
  • Multithreading, vector processors, strip mining, chaining, reduction
  • Snoopy caches, MSI/MESI, directory-based protocols
  • Synchronization, TSO, locks, test-and-set, LR/SC
  • Capstone: your own RV32I core
Capstone
Financial support

Talent, not tuition,
earns a seat here.

A meaningful share of every cohort is fully funded. We evaluate on motivation and aptitude — not institution or income.

Scholarship applications open

Up to 100% fee waiver for the right candidates

Apply alongside your registration. Short answers, no essays. We review on a rolling basis — applying early gives you an advantage.

Merit Scholarship — Grade 1
Highest merit band
100% scholarship
Merit Scholarship — Grade 2
Strong merit band
75% fee waiver
Merit Scholarship — Grade 3
Solid merit band
50% fee waiver
Merit Scholarship — Grade 4
Entry merit band
25% fee waiver
What we look for
Genuine interest in chip design or computer architecture
Clear answer to: what will you build after this?
Commitment to attending live sessions
For need-based: honest financial context
How to apply
The scholarship form is embedded inside registration. After approval, send the matching Razorpay payment link manually for the selected scholarship tier.
No institution required
You don't need to be from a specific college or company. Independent learners, working professionals, and self-taught engineers are all eligible.
Who should apply

Built for engineers
at every stage.

📘
Any-year undergrads
First-year to final-year students from ECE, EEE, CS, or Physics who want a fast start in RTL, processor design, and computer architecture.
🧠
Postgrad researchers
M.Tech and PhD students in computer architecture or SoC design looking to go deeper.
🔧
Working engineers
RTL, verification, or embedded software professionals moving into RISC-V chip design.
⚡
Chip startup builders
Early-stage founders and engineers building custom silicon who need a rigorous foundation fast.
After RISE

What you walk
away with

✓
Learn to design a single-cycle RV32I compliant processor from scratch in Verilog/SystemVerilog.
✓
Deep memory hierarchy knowledge — caches, replacement & write policies, virtual memory, page tables, and TLBs.
✓
Out-of-order execution mastery — scoreboarding, Tomasulo's algorithm, register renaming, and branch prediction (BHT/BTB).
✓
Parallel architecture fundamentals — VLIW, vector processors, multithreading, cache coherence (MSI/MESI), and synchronization primitives.
✓
Open-source EDA fluency — Verilator, Spike, QEMU, GTKWave, and the riscv-tests compliance suite.
✓
RISE certificate of completion and alumni network access — fellow RISE engineers, future cohort updates, and career resources.
RISE Cohort 2
Program at a glance
Full nameRISC-V for Indian Semiconductor Education
Duration6 weeks (1.5 months)
FormatLive online + recordings
Sessions4–5× per week, evenings
PrerequisitesNone · just honest interest
Tools100% open-source
ScholarshipAvailable · apply in form
SeatsLimited · rolling basis
Apply for RISE Cohort 2→
No payment now · commitment-free
Key dates & eligibility

What happens next

Right now
Interest & scholarship applications open
Register and complete the scholarship section if applicable. Rolling review — earlier applications have an advantage.
Within 15 days of applying
Scholarship decisions communicated
All scholarship applicants are notified within 15 days of applying. Merit and need-based awards are announced together.
Before cohort start
Onboarding and tool setup
Confirmed participants receive pre-reading, Linux/WSL setup guides, and cohort workspace access.
TBA · Cohort 2
RISE begins
Six weeks of live sessions, weekly labs, and office hours — ending with your capstone RISC-V core.
Eligibility checklist
✓Any-year undergrads or college students in ECE, EEE, CS, or Physics
✓M.Tech / M.Sc / PhD students in relevant fields
✓Working professionals in hardware or embedded software
✓No prior RISC-V or processor-design experience required
✓Honest interest in chip design, architecture, and RTL
✓Can commit 4–5 evenings per week for 6 weeks
✓Linux machine or Windows with WSL
No prior experience is required. If you are curious about how processors work and want to learn, you are eligible to apply.
Common questions

FAQ

What background do I need?+
No prior RISC-V or processor-design experience is required. Honest interest and a willingness to learn are enough to start.
How many hours per week?+
Expect 8–12 hours per week — roughly 3–4 hours of live sessions and 5–8 hours of labs. Designed to fit alongside a college schedule or part-time work.
Are sessions recorded?+
Yes — all live sessions are recorded and available for the cohort duration. Attending live is encouraged because the Q&A and peer discussions are where a lot of learning happens.
How do I apply for scholarship?+
The scholarship form is embedded in the registration flow — no separate portal. A few short questions. Decisions within 15 days of applying, rolling basis.
What tools will we use?+
The entire toolchain is open-source: Verilator for RTL simulation, GTKWave for waveforms, Spike as the RISC-V ISA reference simulator, QEMU for system emulation, and the RISC-V GCC toolchain. All runs on Linux or Windows WSL.
Is there a certificate?+
Yes. Participants who complete sessions, labs, and the capstone receive a RISE certificate from Semiconductor School. The capstone RTL project is the more valuable portfolio piece.
Will there be more cohorts?+
Yes — RISE is planned as a quarterly program. Registering your interest now keeps you informed even if Cohort 2 fills before you apply.
Is this right for working professionals?+
Absolutely. Evening sessions and weekend lab time fit around day jobs. Scholarship tiers are also open to professionals looking to upskill or transition into chip design.
Cohort 2 · Applications open now

RISE
with RISC-V.

Apply for RISE Cohort 2 through the official form to receive the full program details, scholarship information, and cohort updates.

Apply for RISE Cohort 2
No spam · No commitment · Just RISE updates
Career paths · Semiconductor Engineering

Find your path
in chip design.

Step-by-step roadmaps for every VLSI and semiconductor engineering track — from foundations to industry-ready skills.

Track 01 · RTL Design Engineer
RTL Design
Engineer
The core of chip design — translating architecture specs into synthesisable hardware description language.
⏱ 12–18 months to job-ready📈 High demand🔗 Feeds into: Physical Design, Verification
1
Phase 1 · Foundation
Digital Logic & Boolean Algebra
Before writing a single line of RTL, you need solid foundations in how digital circuits work — gates, combinational and sequential logic, state machines, and timing.
Boolean algebraLogic gates & minimisationCombinational circuitsFlip-flops & latchesFinite state machinesTiming & propagation delayKarnaugh maps
2–3 months
2
Phase 2 · HDL
Verilog & SystemVerilog for Design
Learn to write synthesisable RTL. Understand the design subset of SystemVerilog, simulation constructs, and how code maps to hardware.
Verilog data typesalways_ff / always_combBlocking vs non-blockingParameters & generateInterfaces & modportsSimulation & testbenchesSynthesis constraints
2–3 months
3
Phase 3 · Architecture
Computer Architecture & CPU Design
Understand how processors are built. Pipeline stages, hazard handling, caches, and memory systems. Design a simple RISC-V core end to end.
Instruction set architecturePipeline designHazard detection & forwardingBranch predictionCache designRISC-V implementationOut-of-order concepts
3–4 months
4
Phase 4 · Design Practice
RTL Design Patterns & Protocols
Learn the blocks every RTL engineer designs daily — FIFOs, arbiters, crossbars, clock-domain crossings, and standard bus protocols.
FIFO design (sync/async)Round-robin arbiterClock domain crossingAXI4 / APB / AHBLow-power designReset strategiesLint & CDC checks
2–3 months
5
Phase 5 · Tooling
EDA Tools & Design Flow
Get hands-on with the tools used in industry. Simulation, synthesis, linting, formal property checking. Both open-source and commercial flows.
VCS / Xcelium / VerilatorSynopsys DC / YosysSpyglass (lint/CDC)JasperGold (formal)Makefile flowsGit for RTLWaveform debugging
1–2 months
6
Phase 6 · Portfolio
Capstone Projects & Job Prep
Build portfolio projects that demonstrate real design skill. An open-source RISC-V core, a DMA engine, or a custom accelerator are strong choices.
RISC-V core on GitHubAXI DMA controllerSoC integrationDesign documentationInterview prepOpen-source contributions
2 months
Key tools
SystemVerilogVerilogVCSVerilatorSynopsys DCYosysSpyglassGitPython
Job titles
RTL Design Engineer
Digital Design Engineer
SoC Design Engineer
CPU Architect (senior path)
India salary range
Fresher₹6–12 LPA
3–5 yrs₹18–35 LPA
Senior₹35–60 LPA
RISE covers Phase 3 deeply
Our RISC-V cohort takes you through CPU design, pipelining, and SoC integration — the heart of this roadmap.
Join RISE Cohort 2 →
Track 02 · FPGA Engineer
FPGA
Engineer
Prototyping silicon on programmable fabric — bridging RTL design and real-world hardware deployment.
⏱ 10–15 months to job-ready🔧 Hands-on hardware🔗 Feeds into: RTL, Embedded
1
Phase 1 · Foundation
Digital Logic & FPGA Architecture
Understand what an FPGA actually is — LUTs, flip-flops, block RAMs, DSPs, routing fabric, and how RTL maps to physical resources.
LUT-based logicCLB / slice architectureBlock RAM & URAMDSP blocksPLL & MMCMI/O standardsFPGA families (Xilinx/Intel)
2 months
2
Phase 2 · HDL for FPGA
Verilog / VHDL for Synthesis
Write RTL that synthesises efficiently on FPGAs. Understand resource utilisation, timing closure, and FPGA-friendly coding patterns.
Verilog / VHDLInference-based designRAM inferenceShift register inferenceResource-aware codingSynthesis reports
2–3 months
3
Phase 3 · Constraints & Timing
The hardest FPGA skill — writing timing constraints, reading timing reports, and closing timing on complex designs.
XDC / SDC constraintsSetup & hold analysisClock domain crossingMulticycle pathsVivado timing reportsPipelining for timing
2 months
4
Phase 4 · IP & Interfaces
High-Speed Interfaces & IP Cores
PCIe, DDR, Ethernet, HDMI — FPGA engineers need to work with high-speed interfaces and vendor IP blocks.
AXI4 / AXI-StreamPCIe IPDDR4 controllerEthernet MACSERDES / GTXMIG integration
2–3 months
5
Phase 5 · HLS & Advanced
HLS, Embedded & Acceleration
Vitis HLS, embedded Linux on Zynq, and using FPGAs as accelerators for ML inference, signal processing, and networking.
Vitis HLSZynq / MPSoCEmbedded Linux on FPGADMA & memory mapsOpenCL for FPGAsFPGA ML inference
3 months
Key tools
VivadoQuartusVitis HLSModelSimILAVerilogVHDLPython
Job titles
FPGA Engineer
FPGA Verification Engineer
Hardware Acceleration Engineer
Embedded Hardware Engineer
India salary range
Fresher₹5–10 LPA
3–5 yrs₹15–28 LPA
Senior₹28–50 LPA
RTL skills from RISE apply directly
RISE builds the RTL foundation every FPGA engineer needs — pipelining, bus protocols, and system integration.
Join RISE Cohort 2 →
Track 03 · Verification Engineer
Verification
Engineer
The engineers who ensure chips don't ship with bugs — the largest and fastest-growing role in the semiconductor industry.
⏱ 12–18 months to job-ready📈 Highest hiring volume🔗 Specialise into: Formal, Emulation
1
Phase 1 · Foundation
Digital Design & RTL Reading
A good verification engineer understands design. Learn enough digital logic and RTL to read any block you're tasked with verifying.
Digital logic fundamentalsVerilog / SV readingTiming & clockingSimulation basicsWaveform analysis
2 months
2
Phase 2 · SystemVerilog
SystemVerilog for Verification
OOP concepts, randomisation, functional coverage, and assertions — the core of the SV verification subset.
Classes & inheritanceConstrained randomCovergroups & coverpointsSVA assertionsInterfaces & clocking blocksMailboxes & eventsVirtual interfaces
2–3 months
3
Phase 3 · UVM
Universal Verification Methodology
UVM is the industry-standard framework. Learn base classes, phasing, sequences, and how to build a reusable testbench from scratch.
UVM base classesuvm_agent / driver / monitorSequences & sequencersScoreboard designConfiguration objectsFactory & overridesCoverage closure
3–4 months
4
Phase 4 · Formal & Advanced
Formal Verification & Protocol VIPs
Formal property checking catches bugs simulation misses. Protocol VIPs for AXI, PCIe, USB are essential for block-level verification.
JasperGold / VC FormalProperty specificationAssume / assert / coverAXI VIPProtocol checkingRegression management
2–3 months
5
Phase 5 · Portfolio
Build a UVM Testbench + Job Prep
Verify a real open-source IP block with a complete UVM testbench. RISC-V core verification is an excellent portfolio project.
UVM testbench on GitHubCoverage reportBug reportsInterview prepSV / UVM quiz prep
2 months
Key tools
SystemVerilogUVMVCSXceliumJasperGoldVerdicocotb
Job titles
Design Verification Engineer
UVM Testbench Engineer
Formal Verification Engineer
Emulation Engineer
India salary range
Fresher₹6–12 LPA
3–5 yrs₹18–32 LPA
Senior₹32–55 LPA
RISE builds your DV foundation
Week 6 of RISE covers RISC-V verification with compliance suites — a direct preview of DV engineering work.
Join RISE Cohort 2 →
Track 04 · Physical Design Engineer
Physical
Design Engineer
Taking a synthesised netlist and turning it into a manufacturable layout — the final step before tapeout.
⏱ 14–20 months to job-ready🏭 Close to tapeout🔗 Needs: RTL + STA background
1
Phase 1 · Foundation
CMOS & Digital Design Fundamentals
Physical design starts with understanding how transistors, gates, and standard cells work at the silicon level.
CMOS inverter & gatesStandard cell libraryRTL to gates (synthesis)Netlist conceptsPower, timing, area trade-offs
2 months
2
Phase 2 · STA
Static Timing Analysis
The language of physical design. Setup/hold slack, timing paths, OCV, MMMC — you cannot do PD without deep STA knowledge.
Setup & hold analysisTiming paths & critical pathClock tree conceptsOCV / POCVMMMC cornersSDC constraintsTiming ECO
2–3 months
3
Phase 3 · PnR Flow
Place & Route — Full Flow
The core PD flow: floorplanning, power planning, placement, CTS, routing, and signoff — run end-to-end on a real block.
Floorplanning & partitioningPower ring & meshStandard cell placementClock tree synthesisDetailed routingDRC / LVSInnovus / ICC2
4–5 months
4
Phase 4 · Signoff
Physical Verification & Signoff
Before tapeout, every check must pass. DRC, LVS, antenna rules, IR drop, electromigration, and timing signoff across all corners.
Calibre DRC / LVSAntenna rule fixingIR drop (Voltus)EM analysisPrimetime signoffFill insertion
2–3 months
5
Phase 5 · Open-Source
OpenLane & Sky130 PDK
Run a real tapeout flow using open tools. OpenLane + Sky130 lets you practice the complete PD flow without commercial licenses.
OpenLane flowSky130 PDKOpenROADMagic (DRC/LVS)KlayoutEfabless tapeout
2 months
Key tools
InnovusICC2PrimetimeCalibreVoltusOpenLaneOpenROADTCL
Job titles
Physical Design Engineer
PnR Engineer
STA Engineer
Layout Engineer
India salary range
Fresher₹7–14 LPA
3–5 yrs₹20–38 LPA
Senior₹38–65 LPA
Start with RTL — then go physical
RISE gives you the RTL and SoC integration knowledge that physical design engineers need to understand what they're implementing.
Join RISE Cohort 2 →
Track 05 · DFT Engineer
DFT
Engineer
Design for Testability — the discipline that makes mass chip manufacturing reliable and economically viable.
⏱ 12–16 months to job-ready🔬 Niche & high-value🔗 Needs: RTL + digital logic
1
Phase 1 · Foundation
Digital Logic & Fault Models
DFT starts with understanding what can go wrong in manufactured chips. Fault models are the vocabulary of the field.
Stuck-at fault modelTransition delay faultsBridging faultsFault coverage metricsATPG basicsControllability & observability
2 months
2
Phase 2 · Scan
Scan Design & ATPG
Scan chains are the backbone of digital test. Learn to insert, stitch, and debug scan chains, and use ATPG tools to generate test patterns.
Scan flip-flop architectureScan chain insertionScan compressionATPG pattern generationFault simulationTessent / TetraMAX
3 months
3
Phase 3 · BIST
Memory & Logic BIST Architecture
Built-in self-test for memories and logic — allowing chips to test themselves on the production floor or in the field.
MBIST architectureMarch algorithmsLBIST conceptsBIST controller designRepair logic (BISR)
2–3 months
4
Phase 4 · Advanced DFT
JTAG, IEEE 1149.1 & Boundary Scan
JTAG is the universal debug and test interface. Learn the TAP controller, boundary scan, and how JTAG ties into the full DFT architecture.
JTAG TAP controllerIEEE 1149.1 / 1687Boundary scan cellsIJTAG / ICLDie-to-die testingHierarchical DFT
2–3 months
Key tools
TessentTetraMAXSynopsys DFTVerilogTCLPython
Job titles
DFT Engineer
ATPG Engineer
Test Architecture Engineer
Silicon Debug Engineer
India salary range
Fresher₹6–11 LPA
3–5 yrs₹16–30 LPA
Senior₹30–52 LPA
RTL fluency is a DFT prerequisite
DFT engineers read and modify RTL daily. RISE builds exactly that skill set as your foundation.
Join RISE Cohort 2 →
Track 06 · Analog / Mixed-Signal Engineer
Analog / Mixed-
Signal Engineer
Where physics meets circuits — designing the PLLs, ADCs, DACs, and analog front-ends that every chip needs.
⏱ 18–24 months to job-ready🧪 Highest technical depth🔗 Needs: Circuits + Physics
1
Phase 1 · Foundation
Circuit Theory & Semiconductor Physics
MOSFET physics, small-signal models, biasing, and frequency response — non-negotiable foundations before circuit design.
MOSFET operating regionsSmall-signal modelBiasing & operating pointFrequency response / polesNoise fundamentalsFeedback theory
3 months
2
Phase 2 · SPICE
SPICE Simulation & Circuit Design
Design and simulate analog circuits. Amplifiers, current mirrors, differential pairs — from schematic to simulation to measurement.
SPICE / ngspiceDC / AC / Transient simOp-amp designCurrent mirrorsDifferential pairCadence Virtuoso basics
3–4 months
3
Phase 3 · Key Blocks
PLLs, ADCs, DACs & Bandgap References
The core analog IP blocks found in every SoC — architectures, design trade-offs, and simulation methodology.
PLL architectureVCO designSAR ADCSigma-delta ADCR-2R DACBandgap referenceLDO design
4–5 months
4
Phase 4 · Layout
Custom Layout & Analog Physical Design
Analog layout is a craft. Matching, shielding, guard rings, and parasitic-aware layout directly affect circuit performance.
Virtuoso Layout XLDevice matchingGuard rings & shieldingParasitic extractionPost-layout simulationDRC / LVS
3–4 months
Key tools
Cadence VirtuosoSPICEngspiceSpectreCalibreMatlab
Job titles
Analog Design Engineer
Mixed-Signal Engineer
RF IC Design Engineer
PLL / SerDes Engineer
India salary range
Fresher₹7–14 LPA
3–5 yrs₹22–42 LPA
Senior₹42–80 LPA
Understand the digital context
Analog engineers work at SoC boundaries. RISE gives you the digital and SoC integration context to collaborate effectively.
Join RISE Cohort 2 →
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About us

Semiconductor School

We train engineers and students to design real silicon — starting with an open, RISC-V-based curriculum built for the Indian semiconductor ecosystem.

Who we are

Semiconductor School is an education initiative focused on closing the practical skills gap between academic computer architecture and industry-ready chip design. Our flagship program, RISE (RISC-V for Indian Semiconductor Education), is a live, cohort-based course that takes participants from digital logic fundamentals to a working RV32I processor core, using an entirely open-source toolchain.

What we do

  • Run live, instructor-led cohorts covering RTL design, computer architecture, and RISC-V processor implementation
  • Provide scholarship-backed access so cost is not a barrier to serious learners
  • Build a portfolio-first curriculum — every participant leaves with a working, documented RISC-V core
  • Maintain an alumni network connecting graduates with career resources and future cohorts
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Get in touch

Contact us

Questions about RISE, scholarships, or payments — reach us through any of the channels below.

Email — general
info@semiconductorschool.co.in
Phone
+91-7303422373
Registered address
C-10, Jasola, New Delhi-25

For payment or refund queries

Email info@semiconductorschool.co.in with your registered email and transaction/order ID. See our Refund & Cancellation Policy for timelines.

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Pricing

RISE Cohort 2 — Fellowship value

One transparent fellowship value. Scholarships reduce it — they never raise it.

RISE Cohort 2 · Full Fellowship
Total Fellowship Value: ₹10,000

Includes:

  • 6 weeks of live, instructor-led sessions (4–5× per week, evenings)
  • All session recordings, for the duration of the cohort
  • Lab assignments, code review, and office hours
  • RISE certificate of completion
  • Lifetime alumni network access

Scholarships

A meaningful share of every cohort is fully or partially funded through our merit scholarship program. Scholarships ranging from 100% to 25% of the fellowship value are awarded based on the registration review and selection process. Fee waivers vary according to the scholarship tier granted. See the Scholarship section for details.

Payment methods

Payments are processed securely via Razorpay and support UPI, credit/debit cards, net banking, and popular wallets. We do not store your card or bank details on our servers.

Refunds

Fellowship payments are final. See our full Refund & Cancellation Policy for details.

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Legal

Privacy Policy

Last updated: July 18, 2026

Protecting your private information is our priority. This Privacy Policy applies to the Semiconductor School website and governs the collection, use, and protection of your personal information. Semiconductor School provides live 6-week cohort-based training programs in RISC-V and related semiconductor technologies. By using our website or enrolling in our courses, you consent to the data practices described in this Privacy Policy.

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Legal

Terms & Conditions

Last updated: July 18, 2026

These Terms & Conditions ("Terms") govern your access to and use of the Semiconductor School website and the RISE program. By registering interest, applying for a scholarship, or paying for a cohort, you agree to these Terms.

1. Eligibility

RISE is open to undergraduate students (any year), postgraduate students, and working professionals as described on our RISE Program page. We reserve the right to confirm eligibility before confirming a seat.

2. Program fee and payment

The program fee is displayed on our Pricing page and confirmed at checkout. Payments are processed securely through Razorpay. A seat is confirmed only after successful payment or scholarship approval.

3. Scholarships

Scholarship awards are granted at our sole discretion based on the information submitted in the scholarship application. Providing false or misleading information may result in disqualification.

4. Cancellations and refunds

Cancellation and refund eligibility are governed by our Refund & Cancellation Policy, which forms part of these Terms.

5. Code of conduct

Participants are expected to engage respectfully with instructors and peers, attend live sessions in good faith, and not share paid course material outside the cohort. We reserve the right to remove any participant who violates this code without a refund.

6. Intellectual property

All curriculum content, slides, recordings, and course material remain the intellectual property of Semiconductor School. Participants may use them for personal learning but may not redistribute or resell them.

7. No guarantee of outcomes

While RISE is designed to build real, portfolio-ready skills, we do not guarantee employment, internship, or any specific career outcome as a result of completing the program.

8. Limitation of liability

To the maximum extent permitted by law, Semiconductor School is not liable for any indirect, incidental, or consequential damages arising from your use of this website or participation in the program.

9. Governing law

These Terms are governed by the laws of India. Any disputes will be subject to the exclusive jurisdiction of the courts at [City, State].

10. Contact

Questions about these Terms can be sent to info@semiconductorschool.co.in.

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Legal

Refund & Cancellation Policy

Last updated: July 18, 2026

Refunds are available only before the scheduled cohort start date. Once the cohort has started, no refunds will be provided under any circumstances.

1. Before the Cohort Starts

Participants may request a refund before the official start date of the scheduled cohort by contacting us at info@semiconductorschool.co.in.

2. After the Cohort Starts

Once the scheduled cohort has commenced, all payments become non-refundable. No refunds or partial refunds will be issued for any reason, including non-attendance, withdrawal, scheduling conflicts, or incomplete participation.

4. Exceptional Circumstances

Semiconductor School reserves the right, at its sole discretion, to review exceptional cases. However, submission of a request does not guarantee a refund or any compensation.

3. Contact

For refund-related queries, please contact us at info@semiconductorschool.co.in or visit our Contact page .

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